1. Field of the Invention
The present invention relates generally to a phase-locked loop (PLL), and more particularly to a fast lock-in phase-locked loop.
2. Description of the Background Art
Deep-submicron technology favors digitally intensive designs due to its smallfeature sizes, low supply voltages, large gate leakage currents, etc. The small feature size significantly reduces the area cost of a digital circuit whereas the area of an analog circuit generally does not scale well with the feature size. The low supply voltage limits the headroom of an analog circuit whereas a digital circuit has better noise immunity than the analog counterpart due to its binary operation nature. Even more, the jitter of an analog phase-locked loop (PLL) is usually subjected to leakage currents in a monolithic sub-micron low pass filter. In contrast, a digital low pass filter can completely eliminate this problem to improve the jitter performance.
A number of analog circuits in an analog phase-locked loop are mitigated to digital circuits in an all-digital phase-locked loop. A voltage-controlled oscillator is converted to a digitally controlled oscillator. An analog loop filter is replaced with a digital loop filter. A charge-pump phase-frequency detector can be replaced with an equivalently digital timing-error detector.
Many design variations of an all-digital phase-locked loop arise due to a specific application and a communication specification. A problem common to each of the design variations is the need for the loop to minimize the lock-in time either from start-up or from switching bands. Lock-in time is defined as the time that is required to acquire lock from an initial loop condition. In a traditional phase-locked loop, the lock-in time is proportional to the square of the frequency difference between oscillators' initial and final frequencies. It is also inversely proportional to the cubic of the loop bandwidth.